Plating method for PCB

ABSTRACT

A plating method for a printed circuit board includes: a first step of providing a substrate having a plurality of connection pads and circuit patterns connected to the connection pads; a second step of using some of the circuit patterns provided on a surface of the substrate as a power connection portion and connecting the power connection portion to an external power source; a third step of covering a surface of the substrate excepting the connection pads with a plating resistance resist to shield it; a fourth step of supplying power to the connection pad through the power connection portion and forming a gold-plated layer on the connection pad; and a fifth step of making the power connection portion and the external power source to be electrically short. With this method, a printed circuit board without a power supply line for gold-plating can be obtained.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a printed circuit board and,more particularly, to a plating method for a printed circuit board thatis capable of forming a plated layer without a power supply line forgold-plating at a pad.

[0003] 2. Description of the Background Art

[0004]FIG. 1 is a plane view showing a major part of a printed circuitboard in accordance with a conventional art, and FIG. 2 is a sectionalview showing the major part of a printed circuit board in accordancewith the conventional art.

[0005] As shown in FIGS. 1 and 2, a plurality of printed circuit boards1 a and 1 b are formed on one substrate 1 and as they are separated, theplurality of printed circuit boards 1 a and 1 b are completely produced.

[0006] In the conventional printed circuit board, there are formed at asurface of a base material 8, a plurality of bonding pads 3 on which aplurality of bonding wires are bonded to be electrically connected to asemiconductor chip and a plurality of ball pads 4 on which a solder ballis attached for connection with another printed circuit board. Andcircuit patterns are formed by a single layer or multi-layer inside theprinted circuit board. The bonding pads 3 and the ball pads 4 areelectrically connected to the circuit patterns.

[0007] The bonding pad 3 and the ball pad 4 are gold-plated to heightena bond strength with a gold wire and solder ball. A power supply line 5and a plurality of lead-in wires are formed on the surface of theprinted circuit board for supplying power to the bonding pad 3 and ballpad 4, thus to gold-plate on the pad 3 and 4.

[0008] The power supply line 5 is formed long with a certain width atthe center of the surface of the base material 8, and the lead-in wires6 are branched from the power supply line 5 and connected to the bondingpads 3 or the ball pads 4. Because much current flows in the powersupply line 5, the power supply line 5 is formed wider in its width thanthe lead-line wires 6.

[0009] In the printed circuit board of the conventional art, when poweris supplied to the power supply line 5 from an external source, power issupplied to the bonding pads 3 and the ball pads 4 through the pluralityof lead-in wires 6, performing a gold-plating.

[0010] When the gold-plating process is completed, a process isperformed to separate to a plurality of printed circuit boards. That is,cutting along a router cut line 7 by using a router separates printedcircuit boards 1 a and 1 b.

[0011] At this time, because the router cut line 7 is wider than thepower supply line 5, when the printed circuit boards 1 a and 1 b areseparated, the power supply line 5 is removed so that each bonding pad 3and ball pad 4 is electrically short and only the lead-in wires 6remain.

[0012] However, the plating method for the printed circuit board inaccordance with the conventional has the following problems.

[0013] That is, because the lead-in wires 6 to which the bonding padsand ball pads 4 are connected remain at the surface of the completedprinted circuit boards 1 a and 1 b, when a semiconductor chip is mountedfor use on the printed circuit board, the lead-in wires 6 cause aninterference with peripheral circuits or increase a power consumptionand serve as an element hindering a signal flow, resulting indegradation of a performance of a product.

[0014] In order to solve the problems, as shown in FIG. 3, the lead-inwires are removed by etching method after performing a gold-plating onthe bonding pads 3 and the ball pads 4.

[0015] In this case, however, it is difficult to accurately deposit anetching resist only at the region of the bonding pad 3 and the ball pad4. Also, another problem arises that when the lead-in wires are removed,an etching solution is bound to infiltrate into the bonding pads 3 andthe ball pads 4, removing even the bonding pad 3 and the ball pad 4.Thus, in order to avoid such a problem, the lead-in wire 6 is notcompletely removed, leaving a residual lead-in wire.

[0016] Even in this case, however, existence of the residual lead-inwire 10 causes the same problem as described above, more or less.

[0017] In addition, in the printed circuit board of the conventionalart, it is difficult to process the solder resist because the lead-inwires are removed after the circuit process.

SUMMARY OF THE INVENTION

[0018] Therefore, an object of the present invention is to provide aplating method for a printed circuit board that is capable of reducingpower consumption and improving a performance of a product by providinga printed circuit board with a lead-in wire.

[0019] To achieve these and other advantages and in accordance with thepurpose of the present invention, as embodied and broadly describedherein, there is provided a plating method for a printed circuit boardincluding: A plating method for a printed circuit board comprising: afirst step of providing a substrate having a plurality of connectionpads and circuit patterns connected to the connection pads; a secondstep of using some of the circuit patterns provided on a surface of thesubstrate as a power connection portion and connecting the powerconnection portion to an external power source; a third step of coveringa surface of the substrate excepting the connection pads with a platingresistance resist to shield it; a fourth step of supplying power to theconnection pad through the power connection portion and forming agold-plated layer on the connection pad; and a fifth step of making thepower connection portion and the external power source to beelectrically short.

[0020] In the plating method for a printed circuit board of the presentinvention, the second step includes: coating a photoresist at thesurface of the substrate; removing a portion of the photoresist toexpose the connection pad and exposing some of the circuit patterns toform a power connection portion; and coating an electrolyte layer on thesurface of the substrate for connecting between the power connectionportion and an external power source.

[0021] In the plating method for a printed circuit board of the presentinvention, the electrolyte layer is formed through an electrolessplating method, and the electrolyte layer has a thickness of 0.3˜0.7 μm.

[0022] In the plating method for a printed circuit board of the presentinvention, in the third step, the plating resistance resist is coated atthe surface of the substrate with the electrolyte layer formed thereon,and the fifth step includes: removing the electrolyte layer and theplating resistance resist; and coating a photoresist at the surface ofthe electrolyte layer and the plating resistance resist-removedsubstrate to cover the power connection portion to make power short.

[0023] To achieve the above objects, there is also provided a platingmethod for a printed circuit board including: a first step of providinga substrate having a plurality of bonding pads and ball pads at bothsides thereof and a circuit pattern to which the bonding pads and theball pads are connected; a second step of using some of the circuitpatterns provided at the surface of the substrate as first and secondpower connection portions and connecting the first power connectionportion to an external power source; a third step of covering thesurface of the substrate with the ball pad formed thereon with a platingresistance resist to shield it; a fourth step of supplying power to thebonding pad through the first power connection portion to form agold-plated layer on the bonding pad; a fifth step of making the firstpower connection portion and the external power source to beelectrically short; a sixth step of connecting the second powerconnection portion to the external power source and coating a platingresistance resist at the surface of the substrate with the ball padformed thereon to shield it; a seventh step of supplying power to theball pad through the second power connection portion to form agold-plated layer on the ball pad; and an eighth step of making thesecond power connection portion and the external power source to beelectrically short.

[0024] In the plating method for a printed circuit board of the presentinvention, the second step includes: coating a photoresist at bothsurfaces of the substrate; removing a portion of the photoresist toexpose the bonding pad and the ball pad and exposing some of the circuitpatterns to form first and second connection portion; and coating anelectrolyte layer at the surface of the substrate where the ball pad isformed in order to connect the first power connection portion to anexternal power source.

[0025] In the plating method for a printed circuit board of the presentinvention, the fifth step includes: removing the electrolyte layer andthe plating resistance resist; and coating a photoresist at the surfaceof the electrolyte layer and the plating resistance resist-removedsubstrate to cover the first power connection portion to make powershort.

[0026] In the plating method for a printed circuit board of the presentinvention, the sixth step includes: forming an electrolyte layer at thesurface of the substrate where the bonding pad is formed to electricallyconnect it to the second power connection portion; and coating a platingresistance resist at a surface of the electrolyte layer.

[0027] In the plating method for a printed circuit board of the presentinvention, the eighth step includes: removing the plating resistanceresist and the electrolyte layer; and covering the second powerconnection portion with a photoresist to make the second powerconnection to be short electrically.

[0028] The foregoing and other objects, features, aspects and advantagesof the present invention will become more apparent from the followingdetailed description of the present invention when taken in conjunctionwith the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings, which are included to provide afurther understanding of the invention and are incorporated in andconstitute a part of this specification, illustrate embodiments of theinvention and together with the description serve to explain theprinciples of the invention.

[0030] In the drawings:

[0031]FIG. 1 is a plane view showing one example of a printed circuitboard in accordance with a conventional art;

[0032]FIG. 2 is a perspective view showing the printed circuit board inaccordance with the conventional art;

[0033]FIG. 3 is a plane view showing another example of a printedcircuit board in accordance with the conventional art;

[0034]FIGS. 4A to 4L show sequential process of a method for fabricatinga circuit pattern of a printed circuit board in accordance with apreferred embodiment of the present invention; and

[0035]FIGS. 5A to 5E are plane views sequentially shoring a circuitpattern fabrication process of the printed circuit board in accordancewith the preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] Reference will now be made in detail to the preferred embodimentsof the present invention, examples of which are illustrated in theaccompanying drawings.

[0037]FIGS. 4A to 4L show sequential process of a method for fabricatinga circuit pattern of a printed circuit board in accordance with apreferred embodiment of the present invention.

[0038] A plating method for a printed circuit board of the presentinvention will now be described with reference to FIGS. 4A to 4L.

[0039] First, a substrate 50 is prepared. The substrate 50 includes aninsulation layer 52 formed as at least one or more insulation materialsare thermally compressed and a plurality of circuit patterns 54 stackedinside the insulation layer 52. A metal layer 56 is formed at bothsurfaces of the insulation layer 52, and a plurality of through holes 58are formed to electrically connect the circuit patterns 54 and the metallayers 56 (refer to FIG. 4A).

[0040] The substrate 50 is fabricated through a fabrication process of ageneral multi-layer printed circuit board in which circuit patterns areformed on a plurality of insulation plates, which are stacked by pluralones and thermally compressed.

[0041] A metal-plated layer 60 is formed at the surface of the substrate50 through a plating process. The metal-plated layer 60 is formed at thesurface of the metal layer 56 and at an inner wall of the through hole58.

[0042] The metal-plated layer 60 formed at the surface of the metallayer 56 serves to form circuit patterns 54 and the metal-plated layer60 formed at the inner wall of the through hole 58 serves toelectrically connect the circuit patterns in a follow-up process (referto FIG. 4B).

[0043] Next, the metal layer 56 and the metal-plated layer 60 areselectively removed to form a circuit pattern 62. That is, the circuitpatterns 62 are formed at both surfaces of the substrate 50 through ageneral exposure/development process and an etching process, and some ofthe circuit patterns 62 are used as a bonding pad 64 electricallyconnected to a semiconductor chip and some other circuit patterns areused as a ball pad 66 electrically connected to another printed circuitboard. In general, the ball pad 66 is formed at the opposite side of theside where the bonding pad 65 is formed.

[0044] The bonding pad 64 is connected to a gold wire for electricalconnection with the semiconductor chip mounted at the printed circuitboard, and electrically connected to the circuit pattern 62 formed atthe through hole 58 by the connection pattern 68.

[0045] A solder ball is attached to the ball pad 66 for connection witha different printed circuit board, and the ball pad 66 is electricallyconnected to the circuit pattern 62 formed at the through hole 58 by theconnection pattern 68.

[0046] After the circuit pattern 62, the bonding pad 64 and the ball pad66 are formed at the surface of the substrate 50, a photoresist 70 iscoated at the surface of the substrate 50. The photoresist 70 is toprotect the circuit patterns 62 and is not coated at the connection pads64 and 66 making the bonding pad 64 and the ball pad 66.

[0047] That is, after the photoresist 70 is coated at the entire surfaceof the substrate 50, and the photoresist 70 at the portion of theconnection pads 64 and 66 is removed through an additional process toexpose the connection pads 64 and 66.

[0048] First and second power connection portions 72 and 74 are formedto be used as a path for supplying power to the connection pads 64 and66.

[0049] The first and second power connection portions 72 and 74 areformed by exposing a portion of the circuit pattern 62 by removing aportion of the photoresist 70. That is, a portion of the circuit pattern62 formed connected to the through hole 58 is exposed (refer to FIG.4D).

[0050] A process of forming a gold-plated layer at the connection pads64 and 66 will now be described.

[0051] First, electrolyte layers 76 and 78 are formed at the bothsurfaces of the substrate 50 to connect the first and second powerconnection portions 72 and 74 to an external power source.

[0052] The electrolyte layers 76 and 78 are made of copper and formedthrough an electroless plating method or sputtering (refer to FIGS. 4Eand 5A). Formation of the electrolyte layers 76 and 78 through theelectroless plating method is to make the electrolyte layer 76 to beformed well also at the surface of the photoresist 70.

[0053] The electrolyte layers 76 and 78 are copper-plated through theelectroless plating method and additionally the electrolyte layers 76and 78 are copper-plated through an electrolytic copper plating methodin order to obtain a desired thickness.

[0054] The electrolyte layers 76 and 78 are preferably formed as thin aspossible so as to be easily removed in a follow-up process. For example,preferably, the electrolyte layer 76 and 78 having a thickness of 0.3μm˜0.7 μm.

[0055] And then, a masking process is performed with a platingresistance resist 80 on the opposite side of the side where the bondingpad 64 is formed (refer to FIG. 4F).

[0056] Thereafter, the electrolyte layer 76 of the surface where thebonding pad 64 is formed is removed through an etching method or thelike (refer to FIGS. 4G and 5B). At this time, because the platingresistance resist 80 has been coated at the surface where the ball pad66 is formed, that is, the opposite side of the bonding pad 64, theelectrolyte layer 78 is not removed.

[0057] Besides the above-described method, the electrolyte layer 78 maybe formed only at the surface where the ball pad 66 is formed, while theelectrolyte layer 76 may not be formed at the surface where the bondingpad 64 is formed.

[0058] In this state, when power (P) is supplied from outside throughthe first power connection portion 72, power is supplied to the bondingpad 64 through the electrolyte layer 78, the circuit pattern 62 formedat the through hole 58 and the connection pad 68.

[0059] And then, a gold-plated layer 82 is formed at the surface of thebonding pad 64 (refer to FIG. 4H). The arrow illustrated in FIG. 4Hindicates a power supply path and the circuit pattern 62 is formed in aring shape at the surface of the through hole 58 and electricallyconnects the first power connection portion 72 and the bonding pad 64.

[0060] After the gold-plated layer 82 is completely formed at thebonding pad 64, the plating resistance resist 80 and the electrolytelayer 78 formed at the surface where the ball pad 66 is provided areremoved. And then, the first power connection portion 72 is covered withthe photoresist 70 to make it electrically short (refer to FIGS. 4I, 5Cand 5D).

[0061] After the gold-plated layer 82 is formed at the bonding pad 64, agold-plated layer 92 is formed at the ball pad 66.

[0062] First, electrolyte layers 86 and 88 are formed at both surfacesof the above process-completed substrate 50. Then, the second powerconnection portion 74 and the electrolyte layer 88 are electricallyconnected.

[0063] Next, a plating resistance resist 90 is coated at the surface ofthe electrolyte layer 88 formed at the side where the bonding pad 64 isprovided.

[0064] And then, the electrolyte layer 86 coated at the surface wherethe ball pad 66 is provided is removed through an etching method or thelike (refer to FIG. 4J).

[0065] In this state, external power (P) is applied to the ball pad 66through the second power connection portion 74 to form a gold-platedlayer 92 at the ball pad 66 (refer to FIGS. 4K and 5E).

[0066] The external power (P) is supplied to the electrolyte layer 88and applied to the ball pad 66 through the second power connectionportion 74 connected to the electrolyte layer 88 and the circuit pattern62 formed at the through hole 58 and the connection pad 68.

[0067] After the gold-plated layer 92 is formed at the ball pad 66, theplating resistance resist 90 and the electrolyte layer 88 are removedand the second power connection portion 74 is covered with thephotoresist 70 so that the second power connection portion 74 can beelectrically short.

[0068] As so far described, the method for fabricating a circuit patternof a printed circuit board fabricated through the above-describedprocess has the following advantage.

[0069] That is, because some circuit patterns are used as powerconnection portions and the electrolyte layer is formed at the surfaceof the substrate to transfer an external power to the connection padthrough the power connection portion, a lead-in wire for power supply isnot necessary, and thus, a power consumption can be reduced and aperformance of a product can be improved.

[0070] As the present invention may be embodied in several forms withoutdeparting from the spirit or essential characteristics thereof, itshould also be understood that the above-described embodiments are notlimited by any of the details of the foregoing description, unlessotherwise specified, but rather should be construed broadly within itsspirit and scope as defined in the appended claims, and therefore allchanges and modifications that fall within the metes and bounds of theclaims, or equivalence of such metes and bounds are therefore intendedto be embraced by the appended claims.

What is claimed is:
 1. A plating method for a printed circuit boardcomprising: a first step of providing a substrate having a plurality ofconnection pads and circuit patterns connected to the connection pads; asecond step of using some of the circuit patterns provided on a surfaceof the substrate as a power connection portion and connecting the powerconnection portion to an external power source; a third step of coveringa surface of the substrate excepting the connection pads with a platingresistance resist to shield it; a fourth step of supplying power to theconnection pad through the power connection portion and forming agold-plated layer on the connection pad; and a fifth step of making thepower connection portion and the external power source to beelectrically short.
 2. The method of claim 1, wherein the second stepcomprises: coating a photoresist at the surface of the substrate;removing a portion of the photoresist to expose the connection pad andexposing some of the circuit patterns to form a power connectionportion; and coating an electrolyte layer on the surface of thesubstrate for connecting between the power connection portion and anexternal power source.
 3. The method of claim 2, wherein the powerconnection portion is formed by removing a photoresist from a portion ofthe circuit pattern, and receives power by being connected to theelectrolyte layer.
 4. The method of claim 2, wherein the electrolytelayer is formed through an electroless plating method
 5. The method ofclaim 2, wherein the electrolyte layer has a thickness of 0.3˜0.7 μm. 6.The method of claim 2, wherein the electrolyte layer is formed to have adesired thickness by additionally performing an electrolytic platingmethod on the formed electrolyte layer.
 7. The method of claim 2,wherein, in the third step, the plating resistance resist is coated onthe surface of the substrate formed the electrolyte layer.
 8. The methodof claim 2, wherein the fifth step comprises: removing the electrolytelayer and the plating resistance resist; and coating a photoresist onthe surface of the electrolyte layer and the plating resistanceresist-removed substrate to cover the power connection portion to makepower short.
 9. A plating method for a printed circuit board comprising:a first step of providing a substrate having a plurality of bonding padsand ball pads at both sides thereof and a circuit pattern to which thebonding pads and the ball pads are connected; a second step of usingsome of the circuit patterns provided at the surface of the substrate asfirst and second power connection portions and connecting the firstpower connection portion to an external power source; a third step ofcovering the surface of the substrate with the ball pad formed thereonwith a plating resistance resist to shield it; a fourth step ofsupplying power to the bonding pad through the first power connectionportion for forming a gold-plated layer on the bonding pad; a fifth stepof making the first power connection portion and the external powersource to be electrically short; a sixth step of connecting the secondpower connection portion to the external power source and coating aplating resistance resist at the surface of the substrate with thebonding pad formed thereon to shield it; a seventh step of supplyingpower to the ball pad through the second power connection portion forforming a gold-plated layer on the ball pad; and an eighth step ofmaking the second power connection portion and the external power sourceto be electrically short.
 10. The method of claim 9, wherein the secondstep comprises: coating a photoresist on both surfaces of the substrate;removing a portion of the photoresist to expose the bonding pad and theball pad and exposing some of the circuit patterns to form first andsecond connection portion; and coating an electrolyte layer on thesurface of the substrate where the ball pad is formed in order toconnect the first power connection portion to an external power source.11. The method of claim 10, wherein the first and second powerconnection portion is formed by removing a photoresist from a portion ofthe circuit pattern, and receives power by being connected to theelectrolyte layer.
 12. The method of claim 10, wherein the electrolytelayer is formed through an electroless plating method
 13. The method ofclaim 10, wherein the electrolyte layer has a thickness of 0.3˜0.7 μm.14. The method of claim 10, wherein the electrolyte layer is formed tohave a desired thickness by additionally performing an electrolyticplating method on the formed electrolyte layer.
 15. The method of claim10, wherein, in the third step, the plating resistance resist is coatedon the surface of the substrate with the electrolyte layer formedthereon.
 16. The method of claim 10, wherein the fifth step comprises:removing the electrolyte layer and the plating resistance resist; andcoating a photoresist at the surface of the electrolyte layer and theplating resistance resist-removed substrate to cover the first powerconnection portion to make power short.
 17. The method of claim 9,wherein the sixth step comprises: forming an electrolyte layer at thesurface of the substrate where the bonding pad is formed to electricallyconnect it to the second power connection portion; and coating a platingresistance resist on a surface of the electrolyte layer.
 18. The methodof claim 10, wherein the eighth step comprises: removing the platingresistance resist and the electrolyte layer; and covering the secondpower connection portion with a photoresist to make the second powerconnection to be short electrically.